#Define transistor free

Transfer characteristic is the relation between output current I D and controlling voltage V G S. If 0 < v G S < v P, then 0 < i < I D S S. Here I D S S is a maximum current, when v G S = 0 and v D S > v P. If v G S V b r e a k for breakdown voltage v D S – v p, i D = i D S R D S, R D S = v p 2 2 I D s S ( v G S + v p ) for ohmic region i D = I D S S v p 2 ( v G S + v p ) 2, v D S > v G S + v p, v G S > – v p for saturation region. After this point JFET transistor will go to the saturation mode. Here small channel between two depletion areas will still exist with constant current through is I D S S. At some point drain-source voltage will reach v P level, when these depletion areas will get very close to each other. When v D S is growing, width of depletion areas close of drain is growing as well. Depletion region around p-type areas is wider close to drain because of the voltage distribution between drain and source. Here JFET transistor operates in ohmic mode. Current I D will flow from drain and source (note that electrons will move in the opposite direction). Let’s keep v G S = 0 and apply drain-source voltage v D S > 0.

#Define transistor free

Depletion regions are free from free careers, so there is no current through depletion area. There is thin depletion regions are formed around p-type regions of JFET. JFET transistor is in cut-off mode, and does not conduct any current when both source-gate and drain-source potentials are zero. Here n-type semiconductor is connected to drain and source with ohmic contacts, p-type semiconductors are connected to the gate and connected to each other.

P-type areas are forming the gate, both p-type areas and n-type area are equipped with thin contacts layers. N-type JFET transistor consist of n-type semiconductor with heavily doped p-type regions as shown on the figure. Here current between D and S can be controlled by gate-source voltage.Ĭonstruction of JFET transistor is depicted on the figure below. JFET transistor terminals are drain (D), source (S) and gate (G).

JFET transistor is a three-terminal device, where one of the terminal can control current between two others. This post is about structure, parameters and properties of JFET transistor.